FIFO Memory Modules

A FIFO is a "first in first out" memory buffer between two systems with simultaneous read and write access. It means that the data written into the buffer first comes out of it first. If you’ve ever waited in a line, then you understand how a FIFO functions. FIFOs can be implemented with software or hardware. The choice between a software or hardware solution depends on the application's hard drives and the features desired. FIFO can be either synchronous or asynchronous. The difference between them is that the operation of synchronous FIFO is dependent on the clock, whereas the read/write operation of asynchronous FIFO are alternate to each other.

Synchronous FIFOs are the ideal choice for high-performance systems due to high operating speed. Synchronous FIFOs also offer many other advantages that improve system performance and reduce complexity. These include status flags: synchronous flags, half-full, programmable almost-empty and almost-full flags. These FIFOs also include features such as, width expansion, other memories accesories, and retransmit. Synchronous FIFOs are easier to use at high speeds because they use free-running clocks to time internal operations whereas asynchronous FIFOs require read and write pulses to be generated without an external clock reference. 

An asynchronous FIFO refers to a FIFO where data is written from one clock domain, read from a different clock domain, and the two clocks are asynchronous to each other. It is equipped with control logic that performs management of the read and write pointers, generation of status flags, and optional handshake signals for interfacing with the user logic. The individual read and write ports are fully synchronous, but this FIFO does not require the read and write clocks to be synchronized to each other.

Selecting which FIFO memory works best depends on the performance specifications you require—such as access time, data rate, data setup time, and data hold time. Access time indicates the speed of the memory that begins when the Central Processing Unit (CPU) sends a request to the memory and ends when the CPU receives the data. The data rate—or transfer speed—is the number of bits per second that can be moved internally. The data setup time is the minimum time required for logic levels to be maintained in the input lines, prior to the triggering edge of the clock pulse, in order for the levels to be reliably clocked. The data hold time is the interval required for logic levels to remain on the inputs after the triggering edge of the clock pulse, in order to be reliably clocked into the chip.


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